Hogge pd is deployed to detect the ro frequency disturbance induced by emfi. A system and method are provided for adjusting the phase output of a hogge phase detector. The schottky pair is used as a sampling circuit turned on by the fast step from the step recovery diode, or in the frequency domain, the schottkys act as a mixer to mix the harmonic of the srd. Lock detection algorithm description using signal flow graph. To obtain the specified dc output from the phase detector it is necessary to provide 500ohm dc load impedance. Linear charge pumpplls with the socalled hogge phase detector hogge, 1985 played a long time a favorite role in realizing clockdatarecovery circuits for optical transmission systems.
An electromagnetic fault injection sensor using hogge phase. The hogge phase detector is designed with stscl flipflops ff and stscl xor gates. Bangbang earlylatehold linear pwm pros and cons small quantization noise compatible w digital cdr requires adc simple circuit no quant. Concept creation and design of a parameterizable, fast. Theoretically, any mixer with a dc coupled port could be used as a phase detector. The hogge phase detector two functions transition detection phase detection. Inverse alexander phase detector request pdf researchgate. Hogge detector produces an error signal that is proportional to the instantaneous phase error. This pd consists of two d type flipflops ffs and two exclusiveor xor gates, for detecting the phase shift between two frequencies data and ck, as seen in fig.
Hogge phase detector nonidealities cdr phase shift compensated with a dummy delay element other issues. Phase and frequency analyze plls and dlls in term of phase. Tech, biju patnaik university of technology, 2007 a thesis submitted in partial fulfillment of the requirements for the degree master of science department of electrical engineering college of engineering kansas state university manhattan, kansas. D q clock d q input up down q1 figure 1 q2 you can pick any logic family of your choice. Simplified block diagram of the hogge type phase detector pd.
Delay locked loops and high speed circuit highlights. A nonsequential phase detector for low jitter clock recovery applications by amritraj khattoi b. Transfer characteriscs of the hogge phase detector q example of linear and binary phase detector linear phase detector response paern 11001100 with td0. Note that the setup and hold times as well as the overall delay of the dff directly influence the fine loop performance. Us7088796b2 phase detector customized for clock synthesis. Assume the input data is periodic with a frequency of 1tb hz. The differential output voltages up and do manage the direction of chargepump output current.
If the output of the delay were fed back to the input forming an oscillator. This is a nonlinear device whose output contains the phase difference between the two oscillating input signals. Design and optimization of source coupled logic in multigbits clock and data recovery circuits by david j. Need extremely highspeed xor gates phase skew between tb2 reference and late signals induces a triwave disturbance ripple on. The two halfrate signals are then combined through a multiplexer to obtain fullrate output datastreams, dout. Phase frequency detector non zero average output voltage in case of a frequency difference this drives the vco in the right direction capture rangelock range. Phase detector difference of input and feedback clock phase often built from phase frequency detector pfd 22. Linear dependence between output and phase difference wide frequency acquisition range linear behaviour enables loop parameters calculation drawback. Dec 19, 2006 a system for adjusting the phase signal of a hogge phase detector, the system comprising. Because of its alldigital implementation, the detection methods can be easily integrated into vlsi design process for both asic and. Hogge phase detector with adjustable phase output applied. This performance limitation is due mainly to the inability of the flipflop used in the circuits to settle fast enough. Pulse shaping and clock data recovery for multi gigabit.
It is an essential element of the phase locked loop pll detecting phase difference is very important in many applications, such as motor control, radar and telecommunication systems. Thus, it can achieve 100% detection rate with no false positives. As the detectors are tightly coupled with the logic, they are hard to bypass. Most phase detectors that op erate prop erly with random data e. Therefore, it consumes less power and takes a smaller space. The logic determines which of the two signals has a zerocrossing earlier or more often. Thwarting electromagnetic fault injection attack utilizing. The phase detector enables phase differences to be detected and the resultant error voltage to be produced. Monolithic phaselocked loops for clocking subsystems.
Hogge detector here we have adopted hogge phase detector as shown in figure 2. From lecture 21 similar to frequency synthesizer model exceptno divider phase detector gain depends on the transition density of the input data 1. An electromagnetic fault injection sensor using hogge. The basic delaylocked loop block diagram and timing are shown in fig. Cmos digitalphaselockedloop for 1 gbits clock recovery. The system features a linear hogge phase detector based type2 thirdorder dual loop frequency phase detection architecture. Phase sensitive and phase frequency detectors can be used in. Thephase detector generates errorandrefsignals to eliminate its datadependencyproblemanddead.
Analysis and design of robust multigbs clock and data. Proposed 50t phase frequency detector pfd design consumes significantly low power 18% than other class of pdf. A phase detector customized for clock synthesis unit csu is disclosed. Transfer characteristics of the hogge phase detector. Clock and data recovery the cdr architecture is shown in fig. The output of d flip flop will be delayed copy of input signal. Phase detectors in clock and data recovery circuits. Design and implementation of clock and data recovery. Challenges in the design of highspeed clock and data. The current of all these blocks is controlled by v bn fig. A phase detector or phase comparator is a frequency mixer, analog multiplier or logic circuit that generates a voltage signal which represents the difference in phase between two signal inputs. However, most of these techniques originate from the thought that the phase detectors cannot detect the frequency difference between the received data and the recovered clock in the cdr loops.
Similarly, the xor gates must be able to detect phase differences around a few picoseconds. The hogge phase detector has less elements than other configurations like alexander phase detector. Rate at which the output phase tracks the reference phase lock time, frequency range duty cycle in classic crcs and most source synchronous systems spacing uniformity of multiple edges in oversampled crcs clock wo jitter clock w jitter time domain phase histog ram. Triwaves are produced, resulting in noise on oscillator line clock skew due to internal delays clock and data recovery pll iii. Delay and power analysis of the pfds under discussion are done at different vdd. A tutorial approach to analog phase by angsuman roy yg locked. The hogge phase detector can be used at speeds up to 1ghz in the referenced process, but its performance deteriorates rapidly at modestly higher frequencies. Probably the most widely used is hogge s phase detector 3. In this letter, an improved bangbang phase detector pd for multi gbs clock and data recovery cdr circuits is presented.
These timing parameters play a vital role in designing a system at the transistor level. Clock and data recovery loop using a linear phase detector 20180 pdf. Multilevel signals have both symmetric and asymmetric zero crossings. However, recognizing that a dff produces a delayed replica of the input. In order to improve the accuracy of phase detection current main methods are. A cdr phase comparator is a digital circuit operating at line speed that compares the instants of transition between different levels, or different phases of the received pulses with the instants of transition of the local clock. Hogge phase detector in hogge phase detector, dflipflops are used which have the finite delay in signal path. The ro is used as the watchdog for sensing the transient frequency ripples induced by emfi. The sampling phase detector spd module is a hybrid circuit providing a fast step recovery diode, coupling capacitors and a low barrier schottky pair. An abstract of the dissertation of wenjing yin for the degree of doctor of philosophy in electrical and computer engineering presented on october 20, 2010. Hogge detector phase sampler vco et icp hs charge pump loop filter.
In order to avoid skews in the decision circuit, we choose to sample the data by the clock even in the pd. Need extremely highspeed xor gates phase skew between tb2 reference and late signals induces a triwave disturbance ripple on the control voltage 10 late razavi tb2 ref. Practically, however, mixers often display some very nonideal characteristics e. Hogge phase detector linear phase detector with a data transition and assuming a fullrate clock the late signal produces a signal whose pulse width is proportional to the phase difference between the incoming data and the sampling clock a tb2 reference signal is produced with a tb2 delay. Jitter transfer and jitter tolerance analysis of bangbang. A novel phase detection algorithm is developed and implemented in the combined pd and cp. The comparator shall detect the relative phase and the missing transition. Project description and requirements your project is to do hierarchical design and layout of a hogge phase detector whose block diagram is given in figure 1. Clock and data recoverystructures and types of cdrsthe. More discussions on intrinsic frequency detection capability. Eecs240 lecture 24 linear hogge phase detector eecs240 lecture 24 14 bangbang alexander phase detector edge clock t sym2 away from data derive earlylate from data.
Frequently asked questions about phase detectors an41001. Cdr phase detectors compare the phase between the input. The edge detector doubles the frequency causing the pll to lock to 2tb hz. A novel phase detection algorithm is developed and implemented in the combined pd and cp structure. Design of halfrate clock and data recovery circuits for. The hogge phase detector how can a pd detect data transitions if it samples the data by the vco output. The detectors consist of circuit elements that do actual computation. Request pdf nonidealities in linear cdr phase detectors the effects of circuit nonidealities in a hogge type phase detector are examined. They can be categorised in a variety of ways, but one is given below. Wl of nmos in the proposed design is kept 540180 nm whereas for pmos it is 1620180 nm. Hardware fault attack detection methods for secure.
A delay flip flop dff is used in the phase detector circuit of the clock and data recovery circuit. Since satisfying jitter peaking constraint requires a large capacitor, an external capacitor is inevitable. A dff consists of the three important timing parameters. The project should make use of hierarchical concepts. Rennie a thesis presented to the university of waterloo in ful. Since it is di cult to replicate this sk ew in the decision circuit, the generic cdr arc. A single dff fails to operate as a phase detector if it is used in such a mode. Nonlinear phase detectors provide only sign information regarding the sampling phase error. One major difference is that rather than a voltagecontrolled oscillator vco, a voltagecontrolled delayline is used. The phase detector improves jitter performance by providing minimal activity on vco control lines and pushing ripple frequency to one octave higher, while maintaining wide linear characteristic. Hogge detector this detector has two master slave dflip flops and two exor gates. Recently, it has been discovered in reference 10 that the fullrate hogge linear phase detector. Hogge based emfi detector as a popular linear phase detector, hogge phase detector pd was proposed in 15.
Eecs240 lecture 24 linear hogge phase detector eecs240 lecture 24 14 bangbang alexander phase detector edge clock t sym2 away from data. A phase frequency detector pfd is an asynchronous circuit originally made of four flipflops i. Nonidealities in linear cdr phase detectors request pdf. Plls and dlls cmos vlsi designcmos vlsi design 4th. There is also another type of phase detector called hogge phase detector which operates in a similar way like the phase frequency detector except it is self correcting and independent of the data rate, the temperature or process variations. Design and verification of a pll based clock and data. Design and optimization of source coupled logic in multi. In the case of the basic principles remain unchanged, in order to improve the accuracy of hogge phase detector, 5 proposed a modified hogge phase detector which can auto. It uses both edges of a nyquistrate clock to sample two. Loop filter it is a 2nd order passive loop filter with one external capacitance 144. Mixers as phase detectors most systems which require phase information use mixers somewhere in the measurement or comparison of the phase information. The drawback of the hogge phase detector stems from the looked condition which two xors produce equal pulses. Its loop characteristic is well known gardner, 1980 and the low complexity of the phase detector allows efcient implementation.
No phase difference if outppqyut is rectified at twice the rflo frequency. A nonsequential phase detector for pllbased highspeed. Design and verification of a pll based clock and data recovery circuit 3 fig. While phase detection is effective when initial frequency off. Instead of up and down in pfd, the outputs are named as increase and. Hassan mostafa a graduation project report submitted to the faculty of engineering at cairo university in partial fulfillment of the requirements for the degree of. Clock and data recoverystructures and types of cdrsthe cdr. Design techniques for highperformance digital plls and cdrs abstract approved.
But may take a very long time for a large frequency step multiplier, xor gate, hogge phase detector, alexander phase detector zero average output voltage in case of a frequency difference. Furthermore, an xor phase detectors response can have a larger linear range than a sinusoidal detector mixer. Pavan kumar hanumolu phase locked loops plls are essential building blocks in many communication systems. Note that the dll has many similarities to a phase locked loop pll. Analysis and design of robust multigbs clock and data recovery circuits by david j. If a number of transitions are absent, the output of the multiplier is zero and the.